1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, an arrangement of memory cells.
2. Description of Related Art
In recent years, device variation has been increased in transistors included in an SRAM (Static Random Access Memory) according to miniaturization of a CMOS process. The increase in the device variation causes a problem that memory data is likely to be destroyed in a reading operation in the SRAM. Further, the increase in the device variation causes another problem of a decrease in a reading-rate due to a decrease in a reading current, for example. As a result, a yield ratio of a semiconductor integrated circuit including the SRAM falls. Therefore, a decrease in the device variation by upsizing an SRAM cell is required to keep a certain yield ratio. Thus, this causes a problem of an increase in a circuit scale.
A solution to the above-mentioned problem is provided in “A. Kawasumi et al., “A Single-Power-Supply 0.7V 1 GHz 45 nm SRAM with An Asymmetrical Unit-β-ratio Memory Cell”, 2008 IEEE International Solid-State Circuits Conference, pp-382, 383, and 622 (hereinafter, it is referred as Kawasumi)”. A semiconductor memory device described in Kawasumi includes a plurality of SRAM control circuits (local reading circuit/local writing circuit) that write data to the SRAM cell or read data from the same. Each of the SRAM control circuits controls a plurality of the SRAM cells connected through a common bit-line pair. An SRAM control circuit and a plurality of the SRAM cells controlled thereby constitute an SRAM cell array. Here, in the semiconductor memory device described in Kawasumi, the number of the SRAM cells controlled by an SRAM control circuit is limited. Practically, the number of the SRAM cells controlled by an SRAM control circuit is sixteen. This makes it possible to decrease a load capacity of each bit-line pair, thereby reducing discharge time of the bit-line pairs in the reading operation.
As a result, the problem of the decrease in the reading-rate due to the decrease in the reading current is solved. Further, the problem that the memory data is likely to be destroyed is also solved. A destruction of the memory data in the reading operation is caused due to an electric charge flow from the bit-line charged at a high-voltage-side power supply VDD into a memory node of the SRAM cell holding a low-level. Thus, if it is possible to quickly transmit the memory data to the bit-line as described in Kawasumi, an amount of electric charge flow from the bit-line into the memory node decreases, and the destruction of the memory data can be prevented.